The present invention disclosed herein relates to a method of generating a voltage island for a 3D many-core chip multiprocessor.
In order to successfully apply a 3D stacking technique that has various advantages, power transmission and heat emission worsen due to 3D stacking should be solved. In general, heat generated from a chip is vertically emitted and disappears. However, in a 3D stacking condition, the degree of integration is enhanced, so power consumption increases and heat emission also increases but since generated heat does not easily get out due to a die that is vertically adjacent, heat emission is very important.
Also, in the 3D stacking condition, the number of I/O pins is limited, so power supplied from the outside of a chip to the inside of the chip is also limited but since there is a need to supply more currents to more modules, designing a stable power transmission network is also very important issue.
Since the emission of heat from a circuit is fundamentally determined by power consumption, power management techniques discussed in a 2D integrated circuit (IC) may also be utilized for heat emission management. By generating many voltage islands in one chip, it is possible to operate a part needing high performance at a high voltage and a high frequency and operate a part needing relatively low performance at a low voltage and a low frequency, so decreasing total power consumption. In a multi-core and many-core, several cores are bound to form one voltage island. However, since existing methods address a heat emission issue in a 2D-structure processor, there are difficulties in directly applying them to a 3D condition.